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MITSUBISHI SEMICONDUCTOR MITSUBISHI SEMICONDUCTOR
PS20351-N PS20351-N
TRANSFER-MOLD TYPE TRANSFER-MOLD TYPE INSULATED TYPE INSULATED TYPE
PS20351-N
INTEGRATED POWER FUNCTIONS
500V/3A low-loss 4th generation (planar) IGBT inverter bridge for 3 phase DC-to-AC power conversion.
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
* For upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting, Control circuit under-voltage (UV) protection. Note : Bootstrap supply scheme can be applied. * For lower-leg IGBTS : Drive circuit, Control circuit under-voltage protection (UV), Short-circuit protection (SC). * Fault signaling : Corresponding to a SC fault (Low-side IGBT) or a UV fault (Low-side IGBT). * Input interface : 5V line CMOS/TTL compatible, Schmitt Trigger receiver circuit.
APPLICATION AC100V~200V inverter drive for motor control.
Fig. 1 PACKAGE OUTLINES
HEAT SINK SIDE (3.556) (1) TERMINAL (0.5)
(3.556) (1.656) (0.5)
Dimensions in mm
TERMINAL CODE VUFS (UPG) VUFB VP1 (COM) UP VVFS (VPG) VVFB VP1 (COM) VP VWFS (WPG) VWFB VP1 (COM) WP (UNG) VNO(NC) UN VN WN FO CFO CIN VNC VN1 (WNG) (VNG) P U V W N
(1)
(0.5) DUMMY PIN
(1.778 x 26) (1.778) (6.25) (6.25) (6.25) (8) (8) A
(0.5)
(30.5)
(0.75)
29 30
Type name , Lot No.
(3
.3)
(17.4)
(17.4)
28 27 26 25 24 23 22 21 20 19 18 16 17
15 13 14
12 10 11
987
654
321
D (2
EP
TH
2)
35
34
33
32
31
(7.62 x 4) (41) (42) (49)
(0.5)
(7.62)
(4MIN)
1 2 3 4 5 PCB 6 (1) PATTERN 7 8 (1.9) SLIT 9 (1.8MIN) 10 (PCB LAYOUT) 11 Detail A *Note2 12 13 (5) 14 15 16 17 18 19 20 21 22 23 HEAT SINK SIDE 24 (35 ) 25 26 27 28 29 30 31 32 33 (1.25) 34 (2.5) 35
(6.5)
(10.5)
(1.5)
(1.2)
*Note1:(***) = Dummy Pin.
*Note 2: In order to increase the surface distance between terminals, cut a slit, etc. on the PCB surface when mounting a module.
Sep. 2001
MITSUBISHI SEMICONDUCTOR
PS20351-N
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)
CBW+
CBW-
CBV+ CBV-
CBU-
CBU+
C3 : Tight tolerance, temp-compensated electrolytic type (Note : The capacitance value depends on the PWM control scheme used in the applied system). C4 : 0.22~2F R-category ceramic capacitor for noise filtering.
High-side input (PWM) (5V line) (Note 1,2)
Input signal Input signal Input signal coditioning coditioning coditioning Level shifter Level shifter Level shifter
Protection circuit (UV)
C4 C3
Protection circuit (UV)
Protection circuit (UV)
(Note 6)
DIP-IPM
Inrush current limiter circuit
Drive circuit Drive circuit Drive circuit
P
H-side IGBTS
AC input
(Note 4)
C Z
U V W
M
AC line output
Fig. 3
N1
VNC
N CIN
Drive circuit L-side IGBTS
Z : ZNR (Surge absorber) C : AC filter (Ceramic capacitor 2.2~6.5nF) (Note : Additionally, an appropriate line to line surge absorber circuit may become necessary depending on the application environment.)
Input signal conditioning
Fo logic
SC protection
Control supply Under-Voltage protection
FO CFO Low-side input (PWM) (5V line) (Note 1, 2) FO output (5V line) (Note 3, 5)
Note1: 2: 3: 4:
5: 6:
To prevent the input signals oscillation, an RC coupling at each input is recommended. (see also Fig. 6) By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. (see also Fig. 6) This output is open collector type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 5.1k resistance. (see also Fig. 6) The wiring between the power DC link capacitor and the P/N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22F, high voltage type) is recommended to be mounted close to these P and N1 DC power input terminals. Fo output pulse width should be decided by connecting external capacitor between CFO and VNC terminals. (Example : CFO=22nF tFO=1.8ms (Typ.)) High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit.
VNC VD (15V line)
Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT
DIP-IPM
Drive circuit
P
Short Circuit Protective Function (SC) : SC protection is achieved by sensing the L-side DC-Bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the RC circuit). When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is recommended to stop the system when the Fo signal is received and check the fault.
IC (A)
SC Protection Trip Level
H-side IGBTS
U V W
L-side IGBTS
External protection circuit N1
Shunt Resistor (Note 1)
A
N VNC CIN B
Drive circuit
Collector current waveform
CR
C
Protection circuit
(Note 2)
0 2 tw (s)
Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0s. 2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.
Sep. 2001
MITSUBISHI SEMICONDUCTOR
PS20351-N
TRANSFER-MOLD TYPE INSULATED TYPE
MAXIMUM RATINGS (Tj = 25C, unless otherwise noted) INVERTER PART
Symbol VCC VCC(surge) VCES IC ICP PC Tj Parameter Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature Condition Applied between P-N Applied between P-N Tf = 25C Tf = 25C, instantaneous value (pulse) Tf = 25C, per 1 chip (Note 1) Ratings 350 400 500 3 6 17.8 -20~+150 Unit V V V A A W C
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150C (@ Tf 100C). However, to ensure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) 125C (@ Tf 100C).
CONTROL (PROTECTION) PART
Symbol VD VDB VCIN VFO IFO VSC Parameter Control supply voltage Control supply voltage Input voltage Fault output supply voltage Fault output current Current sensing input voltage Condition Applied between VP1-VNC, VN1-VNC Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS Applied between UP, VP, WP-VNC, UN, VN, WN-VNC Applied between FO-VNC Sink current at FO terminal Applied between CIN-VNC Ratings 20 20 -0.5~VD+0.5 -0.5~VD+0.5 15 -0.5~VD+0.5 Unit V V V V mA V
TOTAL SYSTEM
Symbol Parameter VCC(PROT) Self protection supply voltage limit (short-circuit protection capability) Heat-fin operation temperature Tf Tstg Viso Storage temperature Isolation voltage 60Hz, Sinusoidal, 1 minute, connection pins to heat-sink plate Condition VD = VDB = 13.5~16.5V, Inverter part Tj = 125C, non-repetitive, less than 2 s (Note 2) Ratings 330 -20~+100 -40~+125 1500 Unit V C C Vrms
Note 2 : Tf MEASUREMENT POINT
Al Board Specifications: Dimensions 100 x 100 x 10mm, finishing: 12s, warp: -50~100m
Control Terminals
FWD Chip 18mm 16mm Al Board
IGBT/FWD Chip
Groove IGBT Chip Temp. measurement point (inside the Al board) N W V U P Temp. measurement point (inside the Al board)
Power Terminals
100~200m of evenly applied Silicon-Grease
Sep. 2001
MITSUBISHI SEMICONDUCTOR
PS20351-N
TRANSFER-MOLD TYPE INSULATED TYPE
THERMAL RESISTANCE
Symbol Rth(j-f)Q Rth(j-f)F Parameter Junction-to-heat sink thermal resistance Condition Inverter IGBT part (per 1/6 module) Inverter FWD part (per 1/6 module) (Note 3) (Note 3) Limits Min. -- -- Typ. -- -- Max. 7.0 8.0 Unit C/W C/W
Note 3 : Grease with good thermal conductivity should be applied evenly about +100m~+200m on the contact surface of a DIP-IPM and a heat sink.
ELECTRICAL CHARACTERISTICS (Tj = 25C, unless otherwise noted) INVERTER PART
Symbol VCE(sat) VEC ton trr tc(on) toff tc(off) ICES Parameter Collector-emitter saturation voltage FWD forward voltage Condition IC = 3A, Tj = 25C VD = VDB = 15V VCIN = 0V IC = 3A, Tj = 125C Tj = 25C, -IC = 5A, VCIN = 5V VCC = 280V, VD = VDB =15V IC = 3A, Tj = 125C Switching times Inductive load (upper-lower arm) VCIN = 5 0V VCE = VCES Tj = 25C Tj = 125C Min. -- -- -- 0.4 -- -- -- -- -- -- Limits Typ. 1.7 1.8 1.9 0.9 0.25 0.35 0.90 0.45 -- -- Max. 2.35 2.45 2.6 1.35 -- 0.60 1.35 0.95 1 10 Unit V V s s s s s mA
Collector-emitter cut-off current
CONTROL (PROTECTION) PART
Symbol Parameter Condition Total of VP1-VNC, VN1-VNC VD = VDB =15V VCIN = 5V VUFB-VUFS, VVFB-VVFS, VWFB-VWFS Total of VP1-VNC, VN1-VNC VD = VDB =15V VUFB-VUFS, VVFB-VVFS, VWFB-VWFS VCIN = 0V VSC = 0V, FO = 10k 5V pull-up VSC = 1V, IFO = 1.5mA VSC = 1V, IFO = 15mA (Note 4) Tj = 25C, VD = 15V Trip level Reset level Tj 125C Trip level Reset level Min. -- -- -- -- 4.9 -- 0.8 0.43 10.0 10.5 10.3 10.8 1.0 0.8 2.5 Limits Typ. -- -- -- -- -- 0.6 1.2 0.48 -- -- -- -- 1.8 1.4 3.0 Max. 8.5 1.0 9.7 1.0 -- 0.9 1.8 0.53 12.0 12.5 12.5 13.0 -- 2.0 4.0 Unit mA mA V V V V V V V V ms V V
ID
Circuit current
Fault output pulse width (Note 5) CFO = 22nF Applied between: ON threshold voltage UP, VP, WP-VNC, UN, VN, WN-VNC OFF threshold voltage Note 4 : Short-circuit protection operates only at the low-arms. Please select the value of the external shunt resistor such that the SC trip level is less than 5.1A 5 : Fault signal is outputted when the low-arm short-circuit or control supply under-voltage protective functions operate. The fault output pulse-width tFO depends on the capacitance value of CFO according to the following approximate equation. : CFO = (12.2 10-6 ) tFO [F]
VFOH VFOL VFOsat VSC(ref) UVDBt UVDBr UVDt UVDr tFO Vth(on) Vth(off)
Fault output voltage Short-circuit trip level Supply circuit under-voltage protection
Sep. 2001
MITSUBISHI SEMICONDUCTOR
PS20351-N
TRANSFER-MOLD TYPE INSULATED TYPE
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter Mounting torque Terminal pulling strength Bending strength Weight Heat-sink flatness Condition Mounting screw : M3 Weight 9.8N Weight 4.9N. 90deg bend (Note 6) -- EIAJ-ED-4701 EIAJ-ED-4701 -- -- Min. 0.59 10 2 -- -50 Limits Typ. 0.78 -- -- 20 -- Max. 0.98 -- -- -- 100 Unit N*m s times g m
Note 6: Measurement point of heat-sink flatness
DIP-IPM +- Measurement Range 3mm
Heat-sink - + Heat-sink
RECOMMENDED OPERATION CONDITIONS
Symbol VCC VD VDB VD, VDB tdead fPWM VCIN(ON) VCIN(OFF) Parameter Supply voltage Control supply voltage Control supply voltage Control supply variation Arm shoot-through blocking time PWM input frequency Input ON voltage Input OFF voltage Condition Applied between P-N Applied between VP1-VNC, VN1-VNC Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS For each input signal Tj 125C, Tf 100C Applied between UP, VP, WP-VNC, UN, VN, WN-VNC Limits Min. 0 13.5 13.5 -1 1.5 -- Typ. 280 15.0 15.0 -- -- 15 0~0.65 4.0~5.5 Max. 330 16.5 16.5 1 -- -- Unit V V V V/s s kHz V V
Sep. 2001
MITSUBISHI SEMICONDUCTOR
PS20351-N
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 4 THE DIP-IPM INTERNAL CIRCUIT
VUFB VUFS VP1 UP
HVIC 1
VCC VB HO VS
DIP-IPM
P IGBT1 Di1
IN COM
U
VVFB VVFS VP1 VP
HVIC 2
VCC VB HO VS
IGBT2
Di2
IN COM
V
VWFB VWFS VP1 VP
HVIC 3
VCC VB HO VS
IGBT3
Di3
IN COM
W IGBT4 Di4
LVIC
UOUT
VN1
VCC
IGBT5
VOUT
Di5
UN VN WN
Fo
UN VN WN Fo GND VNO CIN WOUT
IGBT6
Di6
VNC
CFO
VNO(NC) N
CFO
CIN
Note: The IGBTs gates and the HVICs COM terminals are connected to the dummy pins.
Sep. 2001
MITSUBISHI SEMICONDUCTOR
PS20351-N
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 5 TIMING CHARTS OF THE DIP-IPM PROTECTIVE FUNCTIONS [A] Short-Circuit Protection (N-side only)
(For the external shunt resistor and CR connection, please refer to Fig. 3.) a1. Normal operation : IGBT ON and carrying current. a2. Short-circuit current detection (SC trigger). a3. IGBT gate interrupt. a4. IGBT turns OFF. a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor CFO. a6. Input "H" : IGBT OFF state. a7. Input "L" : IGBT ON state. a8. IGBT OFF state.
N-side control input Protection circuit state
a6
a7
SET
RESET
Internal IGBT gate
a2 SC a1
a3
a4 a8 SC reference voltage
Output current Ic Sense voltage of the shunt resistor
CR circuit time constant DELAY
Fault output Fo
a5
[B] Under-Voltage Protection (N-side, UVD)
b1. Normal operation : IGBT ON and carrying current. b2. Under-voltage trip (UVDt). b3. IGBT OFF in spite of control input condition. b4. FO timer operation starts. b5. Under-voltage reset (UVDr). b6. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state
SET UVDr UVDt b2
RESET
Control supply voltage VD
b5
b1 Output current Ic
b3
b6
Fault output Fo
b4
Sep. 2001
MITSUBISHI SEMICONDUCTOR
PS20351-N
TRANSFER-MOLD TYPE INSULATED TYPE
[C] Under-Voltage Protection (P-side, UVDB)
c1. Control supply voltage rises : After the voltage level reachs UVDBr, the circuits start to operate when the next input is applied. c2. Normal operation : IGBT ON and carrying current. c3. Under-voltage trip (UVDBt). c4. IGBT OFF in spite of control input condition (there is no FO signal output). c5. Under-voltage reset (UVDBr). c6. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state UVDBr Control supply voltage VDB
RESET
SET
RESET
c1
UVDBt c2
c5 c3 c4 c6
Output current Ic High-level (no fault output) Fault output Fo
Fig. 6 RECOMMENDED CPU I/O INTERFACE CIRCUIT
5V line
DIP-IPM
5.1k 4.7k UP,VP,WP,UN,VN,WN Fo
CPU
1nF
1nF VNC(GND)
Note : RC coupling at each input (parts shown dotted) may change depending on the PWM control scheme used in the application and on the wiring impedance of the application's printed circuit board.
Sep. 2001
MITSUBISHI SEMICONDUCTOR
PS20351-N
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 7 TYPICAL DIP-IPM APPLICATION CIRCUIT EXAMPLE
C1: Tight tolerance temp - compensated electrolytic type; C2,C3: 0.22~2 F R-category ceramic capacitor for noise filtering
5V line
C2 C1
VUFB VUFS VP1 HVIC1
VCC VB HO VS
DIP-IPM
P
C3
UP
IN COM
U
C2 C1
VVFB VVFS VP1 HVIC2
VCC IN COM VB HO VS
C3
VP V
C2 C1
VWFB VWFS VP1 HVIC3
VCC VB HO VS
M
C P U U N I T
C3
WP
IN COM
W
LVIC
UOUT C3
VN1
VCC
5V line VOUT
UN VN WN Fo VNC
UN VN WN Fo GND VNO CIN CFO WOUT
If this wiring is too long, short circuit might be caused.
N C CFO CIN B C5 R1 Shunt resistor N1 C4(CFO)
15V line
A
The long wiring of GND might generate noise on input signals and cause IGBT to be malfunctioned.
If this wiring is too long, the SC level fluctuation might be large and cause SC malfunction.
Note 1 : To prevent the input signals oscillation, an RC coupling at each input is recommended, and the wiring of each input should be as short as possible (less than 2cm). 2 : By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. 3 : FO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 5.1k resistance. 4 : FO output pulse width should be decided by connecting an external capacitor between CFO and VNC terminals (CFO). (Example : CFO = 22 nF tFO = 1.8 ms (typ.)) 5 : Each input signal line should be pulled up to the positive side of the 5V power supply with approximately 4.7k resistance (other RC coupling circuits at each input may be needed depending on the PWM control scheme used and on the wiring impedances of the system's printed circuit board). Approximately a 0.22~2F by-pass capacitor should be used across each power supply connection terminals. 6 : To prevent errors of the protection function, the wiring of A, B, C should be as short as possible. 7 : In the recommended protection circuit, please select the R1C5 time constant in the range of 1.5~2s. 8 : Each capacitor should be put as nearby the terminals of the DIP-IPM as possible. 9 : To prevent surge destruction, the wiring between the smoothing capacitor and the P&N1 terminals should be as short as possible. Approximately a 0.1~0.22F snubber capacitor between the P&N1 terminals is recommended.
Sep. 2001

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